| 2. | For the different stage resolution sub _ adc with the comparators , it is shown that all sub _ adc work right at clock frequency up to 100mhz with a total power dissipation of 5 . 57mw , while minimal resolution voltage is 10mv , settling time less than 1 . 2ns . when the optimum value of ladder resistance is 1k , the glitches introduced to input signal and the reference 当子adc和构成adc的其他模块进行系统仿真,采样频率为100msps时, adc系统获得不超过1 / 2lsb的dnl ;当正负输入端分别输入频率40 . 902mhz ,相位相反的正弦信号时, sfdr为75 . 4584db 。 |